The invention relates to an inspection system of an optical semiconductor device, a semiconductor device using electron beams or the like, or a circuit pattern of a substrate, and to an image processor therefor. More particularly, the invention is directed to a processor for numerical computation which is used for image processing in the inspection system and the image processor.
Conventionally, processors for performing numerical calculation or data processing have generally improved their processing capabilities by increasing their operational frequencies. Since the improvement by the operational frequency is approaching its physical limit and becomes difficult to achieve, products have been developed increasingly whose processing capabilities are improved by arranging processors in parallel, or by using processors dedicated for specific applications whose processing contents are specialized.
In the high-speed numerical calculation of much data for the image processing or signal processing, a digital signal processor (DSP) including a product-sum operation unit is often used. This DSP includes about one to four adders/subtracters and multipliers, and is designed to read a command stored in a memory, and to perform computation processing using super-scalar architecture with the above-mentioned computing unit according to the command.
Furthermore, some products improve their processing capabilities by arranging von Neumann computers in parallel. This improvement is achieved by dividing and executing processing by a number of computers in parallel, and transmitting and receiving data between the respective computers via a dedicated bus or the like.
As the similar arrangement system of processors, a processor called an array processor or a multi-core processor has been recently developed. This system is constructed by one chip composed of processor cores of a computer, notably the conventional von Neumann computer, which are arranged in parallel. The computer is, for example, a systolic array computer. This has a structure of a connection between a plurality of processors that match a processing algorithm or a computation formula, each processor executing the predetermined computation for every cycle, while transmitting and sending data in a pipeline manner. Some computers have improved their performance by previously connecting processor cores on a matrix, and decentralizing the processing by software.
A system modified from the array processor for effective computation has been proposed. For example, JP-A 312481/2001 discloses a system independently including an array computing unit, and an order controller for effectively executing both computing and controlling operations. JP-A 229378/2001 discloses a system provided with computing elements needed for a normalization correlation operation as an individual circuit, which is an array processor dedicated for an image processing. In the system, the computation is performed by the computing elements arranged in parallel, which constitute the computation pipeline.